1. Field of the Invention
The subject invention relates to motion controllers and, more particularly, to architecture for digital processing circuitry employed in such controllers.
2. Description of Related Art
An important parameter in motion controller design employing digital processing is the length of the sample period within which a motion control algorithm is computed. Because of the complexity of proposed controller algorithms, involving simultaneous control of multiple degrees of freedom, an increasingly shorter sample period has been desired to enable implementation of the algorithms.
The primary problem in prior art motion controller processor architectures is that they do not efficiently use available processor power. In particular, a processor may at times be disabled when its own dual access RAM is being accessed. In other cases, a processor may be required to wait before beginning computing operations while it continues transfers of previous results to memory. In other cases, the location of memory used for dual access or its allocation to several processors controlling several dimensions results in slow operation.